AMD's new Strix Halo uber APU for laptops was already pretty interesting, what with its 256-bit memory bus and monster sized iGPU. Now it turns out that its gestation was a little unusual, with AMD needing four goes at it to get it right and adding some trick tech to its CPU dies in the process.
In an interview with website Chips and Cheese, AMD Senior Fellow Mahesh Subramony revealed some new details about Strix Halo's inner workings. Subramony says AMD "took four iterations" to get Strix Halo right.
That's perhaps not a huge surprise, given Strix Halo had been rumoured for some time and arrived a little later than initial expectations. What is news is that Strix Halo's CPU CCD dies might not be exactly what you expected.
When the APU was first revealed, it looked like AMD had taken a pair of its eight-core Zen 5 CPU CCD dies and crammed them into a package with a new I/O die contain that huge (for an APU) 40 CU iGPU.
Well, that's not the case. Strix Halo has its very own CPU CCDs. They're still Zen 5 based, but AMD has tweaked the CCDs to suit Strix Halo's mobile remit.
For starters, they have a new interconnect. Subramony says the existing interconnect AMD uses between the CCDs in its desktop Zen 5 chips like the Ryzen 9 9950X is fast but has limitations when it comes to power efficiency involving the range of power states that were supported.
The new interconnect for Strix Halo is said to be better in every way. "Low power, same high bandwidth, 32 bytes per cycle in both directions, lower latency," Subramony explains. He also says that switching power states is now "almost instant".
The downside? It's a little more expensive to fabricate than the desktop interconnect. However, Subramony also says that Strix Halo is a full-feature Zen 5 implementation, including the 512-bit FPU.
"I almost joke about it saying it's a Threadripper to put in the palm of your hands. So we didn't pull any punches. These have the 512 bit data path. It is a full desktop architecture," he says.
The only exception to that is clockspeed. "We have binned the parts for efficiency. So it might not hit the peak frequency that you would see on the desktop," Subramony explains.
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He also says that the 32 MB of Infinity cache on the GPU die currently can't be directly accessed by the CPU, it's for the GPU, though that might change in future. "We change that with a flip of a bit but we don't see an application right now where we need to amplify CPU bandwidth," he says.
There are further details about Strix Halo's inner workings in the interview. But suffice to say that what was already one of the most interesting chips in recent years just got a bit more intriguing.
The effort AMD has clearly put into Strix Halo also bodes well for its performance an battery life. If anything, it was the latter that was the greatest unknown with Strix Halo. Could AMD really cram 16 Zen 5 cores and a huge GPU into a power-efficient package?
I was doubtful, for sure. But after learning more about the technology AMD has put into Strix Halo, I can't wait to see just how good AMD's uber APU really is.
